component test
	port (
		a: in STD_LOGIC;
		CLK: in STD_LOGIC;
		clk_en: in STD_LOGIC;
		reset: in STD_LOGIC;
		z: out STD_LOGIC);
end component;


instance_name : test
( a => ,
 CLK => ,
 clk_en => ,
 reset => ,
 z => );
